1. Field of the Invention
The present invention relates generally to processes and methods for fabricating electronic devices from semiconductor materials. More particularly, the present invention pertains to methods and apparatus offering improved process control for fabricating electronic devices having substrates of reduced thickness and enhanced quality.
2. State of the Art
The manufacture of semiconductor devices, commonly termed “dice” or “chips,” encompasses a plurality of major manufacturing stages, each of which typically comprises a number of elements. In general, chip manufacture may be generalized as comprising the stages of crystal growth, wafer preparation, wafer fabrication, wafer sort, and packaging. Wafer sort and packaging may be performed in a different order, or combined into a single manufacturing stage. Typically, a wafer of a semiconductor material, such as silicon, is cut from a large crystal and may have a nominal diameter of up to about 300 mm (12 inches). Although larger bulk semiconductor substrates may have been fabricated, the 300 mm wafer is the largest size wafer currently being phased into commercial production runs by various semiconductor device manufacturers. As cut from a cylinder of semiconductor material transverse to the longitudinal axis thereof, a wafer typically has a thickness considerably greater than the usual end product of the semiconductor fabrication, i.e., singulated semiconductor dice.
A designated “active” surface of a bare wafer may be planarized, as by grinding and chemical-mechanical polishing (CMP) or etching (wet or dry) to a smoothness and planarity required for the formation of integrated circuits therein. A wafer 10 with a planarized active surface 12 and an unthinned back side surface 14 is shown in FIG. 2. The active surface 12 is shown as divided into a plurality of semiconductor dice 16 by “streets” 46. The bare back side surface 14 of the bare wafer 10 is shown in FIG. 3 as unthinned, unpolished and with a rough surface texture with “peaks” 24 and “valleys” 26 having a total amplitude 38 about a back side surface 14. As shown, the wafer 10 is to be thinned from an initial thickness 18 to a final thickness 22 at thinned back side surface 20. The wafer 10 has an overall nominal diameter 28 (FIG. 2) (but for the presence of a wafer flat, as is conventional).
The roughness parameter of a semiconductor surface may be defined in terms of distance between the surface and a straight line extending over the surface between two points. Rt represents the distance between the highest peak and the lowest valley, i.e., the amplitude along the measured length. The Ra surface roughness factor is defined as the arithmetic mean surface roughness measured along a sampling length and is the mean deviation from an imaginary line such that the areas bounded by the surface irregularities are equal above and below this imaginary line. Ra may vary widely, particularly prior to or during rough backgrind of a wafer. The surface finish parameter Ra of the active surface of a polished wafer prior to fabrication is desirably about 2-5 microinches.
An exemplary prior art process for fabricating semiconductor dice 16 from a bare wafer 10 is outlined in FIG. 1. In the industry, a bare wafer 10 (see FIG. 2) is provided in act 100 by in-house manufacture or by purchase. A vendor may preplanarize and polish the active surface 12 in act 102, or it may be performed by the chip manufacturer.
The fabrication act 104 of IC production is concentrated on the “active” surface 12 of the wafer 10, which has undergone preliminary abrasive thinning and planarization/etching acts to planarize and smooth the active surface 12. The active surface 12 typically has a flatness value of about 3-4 μm as measured by the maximum peak-to-valley deviation of the wafer surface from a reference plane extending thereacross. A plurality of sets of identical integrated circuit patterns are simultaneously formed in discrete locations on the active surface 12 by a series of layer deposition and etching processes, as known in the art. The sets of circuit patterns are formed in rows wherein the rows of patterns are separated in X- and Y-axes by streets 46 free of circuitry. Electrical components such as transistors, resistors, capacitors and the like, as well as interconnecting conductors, i.e., “metallization” are typically formed in each pattern. When the active surface 12 of a wafer 10 is not planar (flat), as, for example, due to warping, the use of patterning techniques, such as photolithography, to project a pattern onto the wafer surface results in distorted and out-of-specification image dimensions. Thus, a high degree of planarity is crucial to uniform high-yield production of semiconductor dice.
During fabrication acts 104, various methods of applying a layer of material on the active surface 12 may include screen-coating, stencil-coating, spin-coating, chemical vapor deposition (CVD), and others. Proper layer coverage and subsequent removal acts also depend upon a high degree of active surface planarity and smoothness. Achievement of this degree of planarity and smoothness has been dependent upon the use of wafers with relatively high thickness, in order to counteract internal stresses in the wafer that may lead to warping. Thus, in the current state of the art, a 300 mm (12 inch) wafer may be supplied for fabrication with an initial minimum thickness 18 of about 28-30 mils (about 0.711-0.762 mm).
As the industry moves toward denser circuitry and thinner packages, it has been necessary to reduce the initial thickness 18 of circuitized wafers 10 to a much lower value. Thus, current, conventional practice is to thin wafers to about 4 mils (0.1016 mm). Research and development efforts are working toward the goal of achieving wafers with an ultimate thickness of about 2 mils (0.0508 mm) or less, which would present significant advantages in chip manufacture and offer increased applications. However, the concurrent goal of increasing wafer diameter 28 exacerbates potential problems of wafer cracking, fracturing, and warping. The degree of warping has been generally found to be an inverse function of the square of wafer thickness. It is generally conceded that wafers of 8 inches (200 mm) nominal diameter, and even 5 inches (127 mm), require some sort of mechanical support during backgrinding to a thickness of about 7 mils and during subsequent handling.
Thus, in current practice, upon completion of the fabrication acts 104, a protective coating or layer 48 (FIG. 4), in the form of a polymer layer or of a so-called “backgrind tape,” is applied to the circuitized active surface 12 in act 106 to protect and support the circuitry during a bulk thinning, i.e., backgrinding act 110. The protective coating application is generally illustrated in FIG. 4 and various methods of the prior art are discussed, infra.
For the backgrinding act 110, the active surface 12 with attached protective layer 48 is first mounted in a chuck (not shown) in act 108 to expose the back side surface 14 of wafer 10 for grinding. The backgrinding act 110 is performed to remove extraneous material from the wafer (thinning the wafer 10) from an initial thickness represented by back side surface 14 (see FIG. 4) to a desired thinned back side surface 20, at which point the wafer has a final thickness 22 (see FIG. 3). Typically, this material removal is conducted by a backgrinding act using an abrasive grinding pad or wheel 32 with abrasive particles 36 moved in one or more lateral directions 33 with respect to the plane of wafer 10 (see FIG. 4). Backgrinding generally leaves the back side surface 14 in a rough state, with a significant penetration of, and damage to, the crystal lattice (see FIG. 5). Lateral impact of the abrasive particles 36 against surface features in the form of peaks 24 with forces 34 cause further damage. Damage has been observed at depths of up to about 100 μm into the crystal lattice of a wafer 10. Thus, a further planarization act 112 is typically conducted to reduce back side surface damage from the backgrinding act 110.
Planarization approaches to reducing the back side surface damage due to rough grinding have generally been either to (a) perform a fine polishing by chemical-mechanical polishing (CMP) following backgrinding, or (b) plasma (dry) etch or (less commonly) wet etch the back side surface in act 112. These processes require the rough grinding to be halted prior to attaining the desired final thickness 22, so that the damaged zone of the crystal lattice will be removed in act 112. While these procedures smooth the back side surface 14 to reduce grinding damage, they have little or no beneficial effect upon warping tendencies. In fact, the additional thinning may enhance the proclivity of a wafer for warping. In the past, where wafer thicknesses as low as about 7-20 mils (about 180-500 μm) were considered adequate, the above-described processes worked relatively well. However, fine polishing and/or plasma-etching of back side surfaces of very thin wafers, i.e., having thicknesses of about 4 mils (about 100 μm) or even 2 mils (about 50 μm), is incapable of achieving the desired yield of dice free of unacceptable warping, cracking and even fracturing of the semiconductor material. The problem is greatly exacerbated by using wafers having larger diameters. For example, a wafer may require thinning from an initial thickness of 28 mils to a final thickness of 4 mils. In the thinned state, residual stresses (including backgrinding stresses) in the wafer tend to warp the wafer, a condition also known as “dishing,” which is evident upon removal of a wafer from the chuck and/or upon removal of the protective layer 48 from the active surface 12. Damage due to backgrind thinning may lead to wafer fracture at the time of thinning (backgrinding act 110), upon release from the chuck in act 114, upon removal of a protective layer 48 from the active surface 12 in act 116, during attachment of a removable wafer dicing tape to the wafer in act 118, in die singulation in act 120, and in packaging in act 122. Furthermore, while the rough grinding act is short (time-wise) and relatively inexpensive, the subsequent polishing or etch processes in act 112 are time-consuming and fairly expensive to conduct.
The role of the back side surface of the wafer, if any, is typically that of a mounting surface used to attach an individual semiconductor die to a carrier substrate of some sort. For example, the back side of a semiconductor die may be attached to a lead frame paddle, to an interposer, to a circuit board, to another die, or to some other substrate. In other instances, such as in the case of leads-over-chip packaging or in certain chip-scale packaging configurations, the back side of a semiconductor die may be encapsulated or merely coated. However, as package sizes have decreased, reduction in die (and thus wafer) thickness has been emphasized to reduce the thickness of the resulting packaged electronic device. Wafer thinning and planarization of the back side are required to reduce the wafer thickness to a desired dimension and provide a desired surface smoothness. The continual goal of producing integrated circuits of greater density (memory or logic components per unit volume) necessitates that semiconductor dice be of minimal thickness while retaining sufficient resistance to breakage, warping, electrical degradation and dislocation formation. It is anticipated that reducing wafer thickness to the range of 2 mils or less will become commercially feasible in the near future, making the prevention of such damage even more difficult.
Thinning of a wafer in a controlled manner to a precise endpoint is an exacting process. In addition to simple grinding, other methods of thinning or planarizing the active surfaces of semiconductors include (a) wet etching using an aqueous etchant; (b) dry etching using a dry etchant; (c) sputter-etching to physically remove material; (d) abrasive planarization by, i.e., material removal using a pad in combination with an abrasive slurry; (e) CMP by pad buffing in the presence of a slurry of abrasive particles and a chemical etchant; and (f) sequential combinations of the above processes. Typically, current wafer thinning techniques may require a plurality of wafer grinding and polishing disks. Thinning is typically started with a coarse grinding disk and completed with a fine polishing disk. Because of surface damage caused by coarse grinding, fine polishing is required to remove the damaged layer and provide a smooth planar surface. While the initial grinding act is very short, considerable care, time and expense may be expended in subsequent planarization and polishing of a wafer, although CMP may be conducted relatively rapidly by proper choice of pads, abrasive particles, and etchant.
Conventional approaches to prevention of wafer damage during back side thinning and dicing have been largely concentrated on first providing a supportive protective layer 48 on the active surface to prevent damage to the circuitry. This act 106 is depicted in FIG. 4 and may be carried out in various configurations. For example, in U.S. Pat. No. 5,476,566 to Cavasin, a double-sided tape is used to attach a support layer to the active surface. The tape and substrate may be removed prior to packaging by exposure to UV radiation.
In U.S. Pat. No. 6,534,419 to Ong, electrical connection areas of the active surface are extended upwardly and a polymeric coating is applied to the active surface to cover the active surface. Backgrinding of the back side is then performed, followed by planarization of the active surface to expose the electrical connection areas.
In U.S. Pat. No. 6,506,681 to Grigg et al., a flip-chip wafer is produced by first installing the circuitry including solder bumps on the active surface, applying a molding compound between the bumps, and thinning the wafer by backgrinding. The molding compound is subsequently retained as an underfill material between the bumps.
In U.S. Pat. No. 6,403,449 to Ball, it is disclosed that the application of a protective layer to the active surface prior to backgrinding may actually enhance warping by applying surface tension to the wafer. The reference discloses a method of etching a pattern of grooves in the applied layer to relieve surface tension and decrease warpage.
U.S. Pat. No. 6,258,198 to Saito et al. describes a machine for applying a flexible protective film to the active surface of a wafer prior to backgrinding.
Following application of a protective layer 48 over the active surface 12, the wafer 10 is clamped in a chuck (not shown) in act 108 for backgrinding and planarization in acts 110 and 112, already described. The wafer 10 is mounted to enable these acts to be readily accomplished on the back side surface 14. FIG. 5 depicts the rough back side surface 14 following grinding, and FIG. 6 depicts the back side surface 14 as being relatively planar following fine polishing in act 112.
Following polishing of the back side surface 14, the wafer 10 is removed from the chuck, and dicing tape 50 is attached to the back side surface 14 to enable singulation of wafer 10 without loss or misplacement of individual semiconductor dice 16 (see FIG. 7). This act 118 is well known in the art and may be performed either before or following the removal of protective layer 48 from the active surface 12.
Singulation of the individual semiconductor dice 16 from the wafer 10 typically involves cutting the wafer into rectangular segments along streets 46 (see FIG. 2).
In general and as schematically shown in FIG. 8, a package 30 comprising a singulated semiconductor die 16 is encapsulated in a protective insulating material (encapsulant 52), usually a silicon-filled, transfer-molded, thermoplastic polymeric material, in act 122. Electrical connection elements may also be installed or exposed in this act if not previously effected at the wafer level for attaching the semiconductor die 16 to a carrier substrate. Such connections are not shown in FIG. 8 but are well known in the art to include leads, wire bonds, conductive bumps, balls or columns, and the like.
In U.S. Pat. No. 5,164,815 to Lim, cracking and delamination of the encapsulation layer of a semiconductor package due to high-temperature soldering is purportedly overcome by leaving the die back side as a rough surface to improve adhesion of the packaging material thereto. The invention pertains to packages of relatively high thickness, e.g., about 50 mils (1270 μm) and does not address warping of or damage to the wafer itself. The back side is roughened by a conventional backgrinding process.
In U.S. Pat. No. 5,313,102 to Lim et al., cracking of the encapsulating layer of a semiconductor package due to subsequent exposure to high temperature is addressed by applying a coating of polyimide on the back side of the die prior to packaging. The polyimide is purported to enhance the adhesion of the encapsulation material and reduce cracking thereof. The invention again pertains to packages of high thickness, e.g., about 50 mils (1270 μm) and does not address warping of or damage to the wafer itself.
U.S. Pat. No. 6,184,064 to Jiang et al. teaches the forming of a pattern of contours such as grooves, furrows, etc. in a wafer back side surface to enhance adhesion of an encapsulant or die attach adhesive thereto. The depth of the contours is preferably no greater than about 25 μm.
U.S. Pat. No. 5,583,372 (hereinafter “the '372 patent”) issued to King et al., assigned to the assignee of the present invention, discloses a semiconductor die including a metal layer deposited on the back side surface thereof for enhancing adhesion between the die and a molding compound, i.e., encapsulant compound. The metal layer is substantially oxide free and provides a uniform wetting surface for better adhesion. Furthermore, the '372 patent requires additional materials and fabrication processing, specifically depositing about 50 microinches of copper on the back side surface of the die and approximately 2-3 microinches of palladium over the copper layer.
U.S. Pat. No. 6,279,976 to Ball and assigned to the assignee of the present invention discloses a wafer-handling chuck assembly that uses a vacuum to hold a wafer in a planar configuration during operations thereon.
In view of the foregoing discussion of the problems associated with conventional techniques for backgrinding wafers to an enhanced thinness, which problems are further exacerbated by increasing wafer diameter, it would be advantageous to form such extremely thin wafers while counteracting warping forces. It would also be advantageous to reduce the incidence of wafer fracture and breakage, to heal fracture, scratches and grooves that may occur, and to provide a planar back side surface on the wafer. It would be further desirable to complete the formation of a wafer of enhanced thinness in a configuration that prevents subsequent propagation of lattice defects during die singulation, testing, packaging, attachment to a substrate, and end use. It would also be desirable to enhance the attachment of packaging materials to the back side of a die and to provide an ionic barrier over the wafer back side surface.